MEMS devices are currently pervasively used in the automotive industry and consumer electronics. However, the market for standalone MEMS devices is starting to slow down due to the demand for integrated multi-usage elements, wherein multiple MEMS devices are integrated in a single platform. An example of such integration is multi-degree-of-freedom sensors where micromachined structures, such as accelerometers, gyroscopes and magnetometers are all integrated on the same package. This is to enable smaller form factors, lower cost and lower power consumption, thereby requiring single-die integration.
However, such single-die integration is typically achieved in a hybrid fashion, wherein the die containing the MEMS devices and the application-specific integrated circuit (ASIC), which drives the devices and outputs the signals, are individually fabricated and assembled to form the desired product. The cost associated with such an approach is usually high given that the integration has to be performed at the device level rather than at the wafer level. Moreover, the size tends to be large with a lot of wiring involved.
While there have been platforms, e.g., U.S. Pat. No. 7,104,129 B2, that enable wafer scale integration between the ASIC and the MEMS devices via multiple wafer bonding, the size (especially in the Z direction) still remains large. Moreover, the noise floor from the parasitic effects, which affects the device sensitivity, can still be high. As an example, in the case of capacitive-based sensors, such as commercial accelerometers and gyroscopes, the noise floor can be important due to the parasitic capacitances related to the metallic routings that can span through a whole wafer thickness. This requires additional design considerations at the device level to take this issue into account, which causes more power consumption and bulkier devices.
Such a bottleneck can be resolved by directly fabricating the MEMS elements on the CMOS ASIC substrate. However, silicon is the main material used for the MEMS elements, whose deposition is not compatible with the required thermal budget of the CMOS ASIC substrate, which cannot withstand any process temperatures higher than 450° C. The present invention provides wafer-scale integration in a monolithic fashion through the usage of MEMS structures whose structural material can be deposited directly on the ASIC interconnect layers at temperature lower than 450° C. The subsequent microfabrication steps define the MEMS elements which are anchored to the metal interconnects, thereby providing direct electrical contact. This single chip solution enables: (1) much easier routing to implement optimized mechanical structures, (2) an extremely low cost as no wafer bonding is required, (3) smaller form factors, (4) multiple MEMS elements on a single die, (5) much smaller parasitics providing low noise and higher performance.